[컴퓨터회로] Registers and counter -part A,B

flip-flops are limited because they can store only one bit.

a register is an extension of a flip-flop that can store multiple bits.

4-bit register (Reg-4)

this register uses D flip-flops 

all the flip-flops share a common CLK and CLR signal

basic register but it always input new parellel values when CLK is on the rising edge

add LD input to determine when to load parrellel input values

>clock gating

when LD = 0, the flip-flop C inputs are held at 1. no positive clock edge -> flip flops keep their current values

when LD = 1, the CLK input passes through the OR gate, can receive positive clock edge -> load a new parrellel value from the D3 ~ D0 inputs

• clock gating -> timing problem( delayed a little bit by the OR gate )

a better parallel load

다른 종류 register 도 있음

shift registers

>shift directions

Shift Right의 최상위 비트는 Q0이고, Shift Left의 최상위 비트는 Q3이다. shift direction을 바꾸는 방법은 최상위 비트 (msb)를 결정만 하면 된다

shift registers with parallel load

LD = 0 이면 위의 회로에서 shift right가 작동되고, 

LD = 1 이면 D0~D3 의 new parallel value 가 CLK가 rising edge인 상태에서 load 된다

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Receiving serial data : receive serial data using a shift register

Sending data serially : send data serially with a shift register

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universal shift register

clear : control to clear the register to 0

clock : input to synchronize the operations

shift-right : control to enable the shift right operation

shift-left : control to enable the shift left operation

parallel-load : control to enable a parallel transfer with the n input lines

n parallel input llines

unchanged

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example : serial addition

+ carry out을 JK FF로 저장하는 경우

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Counters (숫자를 세는 회로)

the output value increases by one on each clock cycle.

after the largest value the output back to 0.

Ripple counter

A0 : complement

A1 : A0가 1 -> 0 으로 complement (A0 에 대해 negative edge일때 complement)

A2 : A1가 1 -> 0 으로 complement (A1 에 대해 negative edge일때 complement)

A3 : A2가 1 -> 0 으로 complement (A2 에 대해 negative edge일때 complement)

CLK가 1이 되는 rising edge에서 T에 1이 들어옴

->A0는 원래값에서 complement됨

A0가 1에서 0이 되는 순간,

-> T에 1이 들어와 A1이 complement됨

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Slightly fancier counter

two-bit counter (00,01,10,11) with D FF

single input x.

when x = 0 , the counter value should increment

when x = 1, the counter value should decrement

 

state diagram, -> state table

two-bit counter (00,01,10,11) with JK FF

JK FF의 여기표 이용해서 state table 채우기

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unused states

1 way : fill in don't cares

2 way : self starting counter

more complex counters

a restricted 4 bit counter

starts at some value : when CO = 0, Forces the next state to be loaded from D3-D0

ends at some value : NAND gate forces to load